1. Field of the Invention
The present invention relates generally to an improved data processing system and, in particular, to a method, apparatus and computer program product for data address-based exception handling. Still more particularly, the present invention provides a method, system and computer program product for managing conditional data watchpoints.
2. Description of the Related Art
Currently in data processing, it is typical to have source level code debugging tools provide support for the setting of data address values as a “value of interest” to be tested, monitored, or watched. These data addresses are also known as a “watchpoints”. The watchpoint may be set to a specified user address or user memory location within the effective address space of the process or program being traced and is applicable to either read or write mode operations.
Additional support for the monitoring and management of watchpoints may be provided by means of hardware assist typical with many current versions of processors. This hardware assist typically is in the form of a specific register designed to hold the memory address of the conditional data watchpoint. For example, all PowerPC systems, such as those available from International Business Machines Corporation, since the P4 version have, as a means of hardware support, a data address break register (DABR) to further enable conditional data watchpoint monitoring. The data address break register, or similar component of a processor, capability provides users with the ability to have the hardware of the processor monitor the conditional data watchpoint for a specified address and raise an exception when that address is encountered during instruction processing.
The data address break register, as an example, is a hardware component designed to aid in problem determination dealing with instruction execution. The register may be initialized through known programmatic means as a form of initiator, by the user to a desired value or there may be a hardware specific user interface. The processor hardware then monitors the value placed in the register and provides an event or exception whenever the value is encountered during instruction processing allowing problem determination processing to initiated.
When a data watchpoint has been set with the desired value, any load or store operation to that specified address will cause a hardware generated exception during the execution of a set of instructions in the program code being traced. The hardware exception will also cause the program execution to stop and typically a debugger to be notified. This process is then similar to that which is used in an instruction breakpoint. The debugger may then determine to notify the user based on the user's pre-defined criteria. Typical criteria indicate a user interest in watching for all changes in data values or only specific changes in data values.
While a user is typically interested in conditional data watchpoint monitoring, the user is notified only after the conditions have been met, causing the current watchpoint mechanism to appear to be slow. Every store operation to the specified address causes the debugger to be given control and all threads of the multi-threaded process being examined to stop while the examination of the event continues.
Many processors implement a “trap-after” semantic that provides an indication after the load or store instruction involving the watched memory location has completed. The “trap-after” semantic allows multiple threads updating the watched memory location to complete before the trap handler is called for the thread that caused the watchpoint exception. One approach to this problem is to suspend all but the current thread that hit the watchpoint, then resume all threads after taking action. This approach incurs added overhead of suspending and resuming multiple threads.